Set Reset Latch (SR-Latch)
Until now, we have been looking at combinational circuits. Based on a set of inputs, we have been able to predict the outputs through a circuit. Data is generally drawn as flowing from left to right and top to bottom. But what if we do something different and loop one of our outputs back around to an input? One of two things can happen. We can either land in a meta-stable state, or we can create the following.
In many respects this is a combination circuit still. You can use your truth tables to walk through this. Recall the truth table for the
Alternatively, this can be written with don't care's as follows
Reading this, it tells us that whenever a '1' is input into a
Looking at the SR-Latch above, let's push a few logic values through and see what we get. Start with Set=1 and Reset=0. In this case, we see that a '1' in for Set causes a 0 to be output on the Q' line. This '0' loops back around into the top
Now, let's return our Set line to a '0'. Since we are coming from a set state, the output of the top
Okay, so we Set our latch, let's try to reset it. Assert the Reset line. This '1' value into the top
forcing it to output a '1' regardless of the status of the Reset line (provided Set stays low as shown below).
This behavior can be summarized by the following truth table.
The only other state that we have not tried is when Set and Reset are both set to a '1'. In this case, the '1' into each
SR-Latches can be built to have active-high or active-low inputs and outputs. All combinations are possible. One way to approach this is to push bubbles around the schematic. If we want to make the inputs active low we can put inverters on the input side of the
We can push the bubbles on the outputs of the
Notice that by DeMorgan's this is equivalent to the following