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Set Reset Latch (SR-Latch)

Until now, we have been looking at combinational circuits. Based on a set of inputs, we have been able to predict the outputs through a circuit. Data is generally drawn as flowing from left to right and top to bottom. But what if we do something different and loop one of our outputs back around to an input? One of two things can happen. We can either land in a meta-stable state, or we can create the following.

Set-Reset-Latch

In many respects this is a combination circuit still. You can use your truth tables to walk through this. Recall the truth table for the NOR gate used in this circuit.

BA
Y
00
01
10
11
1
0
0
0
NOR

Alternatively, this can be written with don't care's as follows

BA
Y
00
01
1x
1
0
0
NOR

Reading this, it tells us that whenever a '1' is input into a NOR gate, the result is a '0'.

Looking at the SR-Latch above, let's push a few logic values through and see what we get. Start with Set=1 and Reset=0. In this case, we see that a '1' in for Set causes a 0 to be output on the Q' line. This '0' loops back around into the top NOR gate along with the Reset='0' line causing a '1' to be output. In this configuration, the circuit is said to be set.

Now, let's return our Set line to a '0'. Since we are coming from a set state, the output of the top NOR gate is currently producing a '1'. This value determines the output of the bottom NOR gate regardless of the value of the Set line (look back at your truth table to see this). Since the output from this gate is a '0' and the Reset line is also a '0' the output of the top NOR gate remains at a '1'. This is why the circuit is said to be latched. Once in the Set state, the value of the Set input no longer matters as long as Reset stays at a '0'.

Okay, so we Set our latch, let's try to reset it. Assert the Reset line. This '1' value into the top NOR gate causes it to output a '0'. This output combined with the '0' on the Set line causes the bottom gate to produce a '1' that propagates back to the top NOR

forcing it to output a '1' regardless of the status of the Reset line (provided Set stays low as shown below).

This behavior can be summarized by the following truth table.

SR
QQ'
00
01
10
11
Last QLast Q'
01
10
00
SR-Latch

The only other state that we have not tried is when Set and Reset are both set to a '1'. In this case, the '1' into each NOR gate causes each gate to produce a '0'. There are several problems with this. First the concept of Q = Q' should be illogical. Next, to move to our LastQ state from this state. In logic works, it is impossible to change two switches at once. As a result, you MUST go through the Set or Reset state to get to the LastQ state. In reality, you cannot guarantee that both Set and Reset can move from 11 to 00 without passing through the Set state or the Reset state realiably. As a result, this is considered a bad state and should be avoided at all costs.

SR-Latches can be built to have active-high or active-low inputs and outputs. All combinations are possible. One way to approach this is to push bubbles around the schematic. If we want to make the inputs active low we can put inverters on the input side of the NOR gates and change the name of our signal to be active low as shown below.

We can push the bubbles on the outputs of the NOR gates around on the wire to the input of the NOR gate it connects to. Notice this makes the output Q active low since it is no longer passing through the bubble on the NOR gate. Similarly, we can do the same with the bottom NOR gate causing Q' to be inverted as well. This effectively switches the positions of Q and Q' since (Q')' is Q.

Notice that by DeMorgan's this is equivalent to the following

S'R'
QQ'
11
10
01
00
Last QLast Q'
01
10
00
SR-Latch (active-low)
Last Modified: - Barry E. Mapen