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Data Latch (D-Latch)

The SR-Latch has a bad state that we wish to avoid. One way to ensure this is to link the Set and Reset lines together with a NOT gate.

This only allows the circuit to enter the set or reset states. It cannot enter the Bad state, but... it can no longer enter the Last Q state. What we need to do is recover the functionality of Last Q without getting back into the position where we can have a Bad state. To do this, we add an Enable line that forces the Set and Reset lines to the Last Q state.

This device allows data to pass through when the latch is enabled, and keeps the last value when it is disabled. The following truth table summarizes this behavior

EnD
QQ'
0x
10
11
Last QLast Q'
01
11
D-Latch

In this case, a waveform provides a better explaination since you can more clearly see how the Data passes through while the Enable line is active and the last value is held once enable drops low. The yellow region matches when the enable line is active and therefore Q can change.

Last Modified: - Barry E. Mapen