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Data Flip-Flop (D-FF)

The problem with the latch is that the data can pass through while the latch is enabled. To build reliable sequential circuits, the behavior we want is an edge triggered latch. Instead of allowing data to pass through during the entire interval when the enable is high, we want data to be captured as during the very brief transition from low to high. This is known as a rising edge. Similarly, falling edges are when a signal moves from high to low. Using two latches, edges can be used as the point in time when data passes through a flip-flop.

To understand this device, it is most helpful to look at the waveform associated with this device. The yellow areas are when each of the latches can transition.

Looking at the overall result, notice that the value of D passes through to Q as CLK0 rises.

Now you might be asking... what happens if D changes at the same time the rising edge of CLK0 occurs? Good question. The answer: it depends. For now, we will be working with synchronous designs and we will guarantee that this condition never occurs. We will talk about asynchronous designs (where they are useful) and the associated methods for dealing with this problem.

Last Modified: - Barry E. Mapen